Optimal Powers up Thermal Analysis in TSMC Reference Flow 8.0
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Optimal Corporation™ has announced IC package thermal analysis for TSMC’s Reference Flow 8.0. TSMC’s latest reference flow addresses 45-nanometer designs and features statistical timing analysis for intra-die variation, automated DFM hot-spot fixing and new dynamic low-power design methodologies. Reference Flow 8.0 is the latest generation of TSMC’s design methodology that can increase yields, lower risks and improve design margins.
“TSMC and Optimal have been working together since Reference Flow 5.0 to address the issue of Chip-Package co-design. In Reference Flow 8.0, we extended that collaboration to ensure the chip will operate correctly in its packaged thermal environment,” said Dave DeMaria, Optimal’s chief executive officer.
“TSMC’s Reference Flow 8.0 is an industry benchmark that we are proud to be associated with through our PakSi-TM thermal analysis product,” DeMaria added.
“At 45-nanometers, IC packaging thermal issues are critical,” said Kuo Wu, deputy director of design service marketing at TSMC. “With TSMC’s Reference Flow 8.0 and Optimal’s PakSi-TM, designers can verify that finished silicon chip designs can work within a thermal environment of the selected package while still satisfying performance and yield goals.”
According to Optimal, PakSi-TM allows package engineers to save time and money by determining the thermal and mechanical characteristics of the IC package before a design is committed to fabrication.
Developed by a team of engineers skilled in complex IC package design, PakSi-TM is a tool with ease-of-use, while taking into account die power distribution, material properties, and the surrounding PCB environment in order to predict thermal resistance and temperatures for the die to package to ambient environment.
